VLSI CMOS interview questions and answers 2016

VLSI CMOS interview questions and answers 2016.

1. what is the difference between mealy and moore state-machines

2. How to solve setup & Hold violations in the design
To solve setup violation

1. optimizing/restructuring combination logic between the flops.

2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx]

3. Tweak launch-flop to have better slew at the clock pin, this
will make CK->Q of launch flop to be fast there by helping fixing
setup violations
4. Play with skew [ tweak clock network delay, slow-down clock to
capturing flop and fasten the clock to launch-flop](otherwise called as Useful-skews)
To solve Hold Violations

1. Adding delay/buffer[as buffer offers lesser delay, we go for spl
Delay cells whose functionality Y=A, but with more delay]

2. Making the launch flop clock reaching delayed

3. Also, one can add lockup-latches [in cases where the hold time
requirement is very huge, basically to avoid data slip]

3. What is antenna Violation & ways to prevent it
During the process of plasma etching, charges accumulate along the metal strips. The
longer the strips are, the more charges are accumulated. IF a small transistor gate
connected to these long metal strips, the gate oxide can be destroyed (large electric field
over a very thin electric) , This is called as Antenna violation.

The ways to prevent is , by making jogging the metal line, which is atleast one metal
above the layer to be protected. If we want to remove antenna violation in metal2 then
need to jog it in metal3 not in metal1. The reason being while we are etching metal2,
metal3 layer is not laid out. So the two pieces of metal2 got disconnected. Only the piece of metal connected to gate have charge
to gate. When we laydown metal3, the remaining portion of metal got charge added to
metal3. This is called accumulative antenna effect.

Another way of preventing is adding reverse Diodes at the gates

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