# UPPCL Electronics Sample Question Paper 2019-20 | UPPCL Electronics Exam

UPPCL Electronics Sample Question Paper 2019-20 | UPPCL Electronics Exam.

Uttar Pradesh Power Corporation Limited  (UPPCL Electronics) 2019-20  UPPCL Electronics Model Question Papers 2019-20 UPPCL Electronics Sample Question papers UPPCL Electronics Mock Test Question Paper for 2019-20 Exam, This UPPCL Electronics Question are based on the syllabus but here some of the question may out of syllabus, just for your better exam UPPCL Electronics Exam preparation.

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## UPPCL Electronics Sample Question Paper 2019-20 | UPPCL Electronics Exam

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18. For one of the following conditions, clocked J-K flip-flop can be used as DIVIDE BY 2 circuit where the pulse train to be divided is applied at clock input.
a) J = 1, k = 1 and the flip- flop should have active HIGH inputs
b) J = 1, k = 1 and the flip- flop should have active LOW inputs
c) J = 0, k = 0 and the flip- flop should have active HIGH inputs
d) J = 1, k = 1 and the flip- flop should be a negative edge triggered one

19 Number of comparators needed to build a 6-bit simultaneous A/D converter is
a) 63 b) 64 c) 7 d) 6

The AID converter used in a digital voltmeter could be (1) successive approximation type (2) Flash converter type (3) Dual slope converter type. The correct sequence in the increasing order of their conversion time taken is
a) 1, 2, 3 b) 2, 1, 3
c) 3, 2, 1 d) 3, 1, 2

Which of the following binary number is equal to octal number 66.3
a) 101101.100 b) 1101111.111
C) 111111.1111 d) 110110.011

A 4-bit presetable UP counter has preset input 0101. The preset operation takes place as soon as the counter reaches 1111. The modulus of the counter is
a) 5 b) 10 c) 11 d) 15

. A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will be
a) 25 ns b) 50 ns c) 75 ns d) 100 ns

If a counter having 10 FFs is initially at 0, what count will if hold after 2060 Pulses
a) 000 000 1100 b) 000 001 1100
c) 000 001 1000 d) 000 000 1110

Memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is
a) 2 b) 4 c) 8 d) 16

In time division multiplexing
a) Time is doubled between bits of a byte
b) Time slicing at CPU level takes place
C) Total time available in the channel is divided between several users and each users is allotted a time slice.
d) None of the above

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